US 12,462,891 B2
Multi-level cell maintenance operations
Giuseppe Cariello, Boise, ID (US); Nitul Gohain, Karnataka (IN); and Jameer Mulani, Karnataka (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2024, as Appl. No. 18/417,737.
Claims priority of provisional application 63/484,729, filed on Feb. 13, 2023.
Prior Publication US 2024/0274215 A1, Aug. 15, 2024
Int. Cl. G11C 29/42 (2006.01)
CPC G11C 29/42 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
read, during a first portion of a maintenance operation, first data from a first block of memory cells of a first memory device of the one or more memory devices, the maintenance operation to transfer the first data from the first block to a second block using a two-pass write operation;
perform, during the first portion of the maintenance operation, a first error control operation on the first data to correct the first data based at least in part on reading the first data from the first block of memory cells;
store second data associated with the first error control operation to a portion of the first memory device based at least in part on performing the first error control operation on the first data read from the first block of memory cells, the second data comprising one or more parameters associated with the first error control operation or a location of a third block of memory cells to which the first data is written based at least in part on whether a condition associated with the first error control operation satisfies a threshold; and
perform, during a second portion of the maintenance operation, a second error control operation using the second data associated with the first error control operation stored to the portion of the first memory device.