US 12,462,889 B2
Memory verification using processing-in-memory
Robin Conradine Knauerhase, Portland, OR (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 27, 2022, as Appl. No. 18/146,558.
Prior Publication US 2024/0212777 A1, Jun. 27, 2024
Int. Cl. G11C 29/14 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/14 (2013.01) [G11C 2029/1208 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory of a memory module, the memory including memory testing logic; and
an in-memory processor disposed in the memory module, the in-memory processor configured to receive the memory testing logic from the memory, execute the memory testing logic in the in-memory processor to test the memory, and output an indication of a detected fault based on testing the memory.