US 12,462,888 B2
Non-volatile memory with neighbor plane program disturb avoidance
Jiahui Yuan, Fremont, CA (US); and Lito De La Rama, San Jose, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 29, 2023, as Appl. No. 18/361,843.
Claims priority of provisional application 63/510,578, filed on Jun. 27, 2023.
Prior Publication US 2025/0006288 A1, Jan. 2, 2025
Int. Cl. G11C 29/12 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/12005 (2013.01) [G11C 29/1201 (2013.01); G11C 29/46 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
multiple separate planes, each plane comprises non-volatile memory cells and word lines; and
a control circuit connected to the planes, the control circuit is configured to:
ramp up voltage on selected word lines in multiple planes,
concurrently test the multiple planes for a voltage leak in any of the multiple planes using the voltage being ramped up on the selected word lines in the multiple planes,
if no voltage leak is detected, then concurrently program data into memory cells connected to the selected word lines in the multiple planes, and
if a voltage leak is detected, separately test each plane of the multiple planes for a voltage leak at its respective selected word line and concurrently program data into memory cells connected to the selected word lines in planes of the multiple planes without a detected voltage leak while isolating a plane of the multiple planes with a detected voltage leak.