| CPC G11C 29/022 (2013.01) [G11C 7/1096 (2013.01); G11C 29/14 (2013.01); G11C 29/52 (2013.01); G11C 2029/1202 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines; and
control logic configured to control an input/output operation of the memory cell array, and
wherein, responsive to receiving a memory defect detection command from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage, and
wherein, responsive to receiving a mode register read command from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.
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