US 12,462,886 B2
Method for programming a memory device to reduce retention error
Haibo Li, Wuhan (CN); Man Lung Mui, Wuhan (CN); and Yu Wang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jul. 24, 2023, as Appl. No. 18/225,575.
Application 18/225,575 is a continuation in part of application No. 17/318,992, filed on May 12, 2021, granted, now 12,033,708.
Application 17/318,992 is a continuation of application No. 16/371,130, filed on Apr. 1, 2019, granted, now 11,037,642.
Application 16/371,130 is a continuation of application No. PCT/CN2019/075549, filed on Feb. 20, 2019.
Prior Publication US 2024/0006004 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/3486 (2013.01) [G11C 16/08 (2013.01); G11C 16/3459 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory cells, comprising:
a first set of memory cells configured to be programmed into a first set of programming states each of which is not lower than a first predetermined programming state; and
a control circuit coupled to the plurality of memory cells and configured to:
perform a first program pass to program the first set of memory cells;
continue to program at least a first memory cell from the first set of memory cells with one or more first programming voltages, wherein a threshold voltage of the first memory cell is greater than a first verification voltage that corresponds to a first programming state of the first memory cell; and
perform a second program pass to program the first set of memory cells after the first memory cell is continued to be programmed with the one or more first programming voltages.