US 12,462,885 B2
Memory device preventing generation of under-programmed memory cell, memory system including the same and operating method thereof
Sung Yong Lim, Icheon-si (KR)
Assigned to SK hynix INc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 4, 2024, as Appl. No. 18/626,748.
Application 18/626,748 is a continuation of application No. 17/670,267, filed on Feb. 11, 2022, granted, now 12,009,037.
Claims priority of application No. 10-2021-0125825 (KR), filed on Sep. 23, 2021.
Prior Publication US 2024/0257886 A1, Aug. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory block including a plurality of pages coupled to a plurality of word lines;
a peripheral circuit configured to perform a plurality of program loops sequentially for programming the plurality of pages, each including a program pulse operation of applying a program voltage to a selected word line among the plurality of word lines and a verify operation, wherein a level of the program voltage increases through the plurality of program loops, and the peripheral circuit applies a verify voltage to the selected word line and applies a verify pass voltage to unselected word lines among the plurality of word lines during the verify operation; and
a control logic circuit configured to control the peripheral circuit to increase, while at least part of the plurality of program loops are in progress, a level of the verify pass voltage applied to the unselected word lines, wherein the unselected word lines, to which the verify pass voltage of which the level increases is applied, include both word lines coupled to a programmed page and an erase page among the plurality of pages.