US 12,462,884 B2
Page buffer circuit and read operation method of memory
Jae Woong Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Sep. 1, 2023, as Appl. No. 18/459,447.
Claims priority of application No. 10-2023-0060998 (KR), filed on May 11, 2023.
Prior Publication US 2024/0379177 A1, Nov. 14, 2024
Int. Cl. G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/1039 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A page buffer circuit comprising:
a sensing node;
a first sensing latch configured to sense and store a voltage level of the sensing node at a first time point during an evaluation period of evaluating the sensing node according to a voltage level of a bit line;
a second sensing latch configured to sense and store the voltage level of the sensing node at a second time point during the evaluation period; and
a pre-charge unit configured to pre-charge the sensing node before the evaluation period,
wherein the pre-charge unit is configured to use a first power supply voltage to pre-charge the sensing node, and the first and second sensing latches are each configured to use a second power supply voltage having a different voltage level from the first power supply voltage, and
wherein a voltage level of the second power supply voltage is adjustable.