US 12,462,882 B2
Semiconductor memory including a current comparison readout circuit
Ming Gu, Wuxi (CN); Hao Wang, Wuxi (CN); Shuming Guo, Wuxi (CN); Youhui Li, Wuxi (CN); Bin Chen, Wuxi (CN); and Yongqiang Hu, Wuxi (CN)
Assigned to CSMC TECHNOLOGIES FAB2 CO., LTD., Jiangsu (CN)
Appl. No. 17/928,333
Filed by CSMC TECHNOLOGIES FAB2 CO., LTD., Jiangsu (CN)
PCT Filed Apr. 27, 2021, PCT No. PCT/CN2021/090083
§ 371(c)(1), (2) Date Nov. 29, 2022,
PCT Pub. No. WO2022/110636, PCT Pub. Date Jun. 2, 2022.
Claims priority of application No. 202011374365.2 (CN), filed on Nov. 30, 2020.
Prior Publication US 2023/0215503 A1, Jul. 6, 2023
Int. Cl. G11C 16/28 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/28 (2013.01) [G11C 16/08 (2013.01); G11C 16/30 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory, comprising:
a first memory array including a plurality of memory cells;
a second memory array including a plurality of memory cells;
a comparison readout circuit including a first port and a second port, the first port being configured to receive an electrical signal of a read memory cell, the second port being configured to receive a reference electrical signal, the comparison readout circuit being configured to compare the electrical signal of the read memory cell with the reference electrical signal, so as to obtain storage information of the read memory cell;
a first column decoder coupled to the first memory array and the comparison readout circuit, configured to select a bitline (BL) corresponding to the read memory cell when a memory array selection signal enables the first memory array, and output the electrical signal of the memory cell to the first port through the BL, and further configured to couple a first BL of the first memory array to the second port when the memory array selection signal does not enable the first memory array; and
a second column decoder coupled to the second memory array and the comparison readout circuit, configured to select a BL corresponding to the read memory cell when the memory array selection signal enables the second memory array, and output the electrical signal of the memory cell to the first port through the BL, and further configured to couple a second BL of the second memory array to the second port when the memory array selection signal does not enable the second memory array wherein
the first column decoder and the second column decoder each include an A×B two-level decoder, each two-level decoder includes B first selection switches and A second selection switches, an input terminal of each second selection switch is coupled to a BL, each second selection switch is configured to turn on the coupled BL when enabled, each address decoder controls each second selection switch through A second-level switch signals, and each second-level switch signal controls turn-on of B consecutive address BLs;
an input terminal of each first selection switch is coupled to output terminals of the A second selection switches, an output terminal of each first selection switch is coupled to the first port, and each address decoder controls turn-on of the B first selection switches through B first-level switch signals in a one-to-one corresponding manner; and
each of the first selection switches is controlled by column selection address low-order decoding output, and each of the second selection switches is controlled by column selection address high-order decoding output.