US 12,462,881 B2
Charge loss compensation during read operations in a memory device
Vivek Venkata Kalluru, San Jose, CA (US); Michele Piccardi, Cupertino, CA (US); Taehyun Kim, San Jose, CA (US); and Theodore T. Pekny, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 2, 2024, as Appl. No. 18/762,228.
Application 18/762,228 is a continuation of application No. 17/669,073, filed on Feb. 10, 2022, granted, now 12,057,174.
Claims priority of provisional application 63/260,332, filed on Aug. 17, 2021.
Prior Publication US 2024/0355397 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01); G11C 16/28 (2013.01); G11C 16/3418 (2013.01); G11C 16/3422 (2013.01); G11C 16/3431 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of wordlines; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a read operation on the memory array;
detecting a change in string resistance in the memory array;
determining whether the change in string resistance is attributable to a presence of a partially programmed block in the memory array; and
responsive to determining that the change in string resistance is attributable to the presence of the partially programmed block in the memory array, performing the read operation using default read voltage levels to read data from the memory array.