US 12,462,880 B2
Matrix-vector multiplications based on charge-summing memory cell strings
Jonas Doevenspeck, Herent (BE); Maarten Rosmeulen, Ghent (BE); and Stefan Cosemans, Leuven (BE)
Assigned to Imec vzw, Leuven (BE)
Filed by IMEC VZW, Leuven (BE)
Filed on Dec. 21, 2023, as Appl. No. 18/392,161.
Claims priority of application No. 22215794 (EP), filed on Dec. 22, 2022.
Prior Publication US 2024/0212763 A1, Jun. 27, 2024
Int. Cl. G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An in-memory compute device for performing analog multiply-and-accumulate operations on a set of data inputs and a set of weight inputs, the in-memory compute device comprising:
a string of serially connected memory cells formed over a semiconductor channel structure, wherein each memory cell comprises a programmable threshold transistor adapted for permanently storing a threshold voltage representing a respective weight of the set of weight inputs;
a source junction controllably connectible to one end of the string of serially connected memory cells via a string select switch;
a readout circuit including a sense node controllably connectible to one end of the string of serially connected memory cells via a charge transfer switch, wherein the readout circuit is configured to buffer transferred charge packets from the string of serially connected memory cells as a charge sum signal on the sense node and convert the charge sum signal into an output voltage; and
control circuitry configured for:
applying a pass mode signal to control gate terminals of the respective memory cells of the string to cause the memory cells of the string to be switched on, irrespective of the programmed threshold voltages;
applying data input signals representative of the set of data inputs to the control gate terminals of the respective memory cells of the string, wherein applied data input signals representing binary zeroes cause memory cells of the string to be switched off;
applying stop signals to the control gate terminals of the respective memory cells of the string to cause the remaining memory cells of the string to be switched off;
enabling the string select switch to connect the source junction to the string of memory cells while applying the pass mode signal and the data input signals; and
enabling the charge transfer switch to connect the sense node to the string of memory cells while applying the stop signals,
wherein the data input signals and the stop signals are applied sequentially according to each memory cell's position along the string.