US 12,462,879 B2
Memory device and operating method of the memory device
Dong Uk Lee, Icheon-si Gyeonggi-do (KR); Yun Cheol Kim, Icheon-si Gyeonggi-do (KR); and Hae Chang Yang, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Apr. 6, 2023, as Appl. No. 18/296,789.
Claims priority of application No. 10-2022-0132326 (KR), filed on Oct. 14, 2022.
Prior Publication US 2024/0127892 A1, Apr. 18, 2024
Int. Cl. G11C 16/16 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/3495 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block including a plurality of sub-blocks;
a peripheral circuit configured to perform a first program operation in a first manner in a first sub-block, among the plurality of sub-blocks, and configured to perform a second program operation in a second manner in a second sub-block, among the plurality of sub-blocks; and
a control circuit configured to, when a program number of the second program operation that is performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for threshold voltages of memory cells included in the first sub-block.