| CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/24 (2013.01)] | 20 Claims |
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1. A memory device comprising:
first memory cells connected to first channels adjacent to a plurality of slits, among a plurality of channels that pass through a plurality of word lines and are separated by the plurality of slits;
second memory cells connected to second channels farther from the plurality of slits than the first channels among the plurality of channels;
a read and write circuit configured to perform a sensing operation on the first memory cells and the second memory cells connected to a selected word line among the plurality of word lines; and
a program controller configured to control the read and write circuit to perform the sensing operation during different sensing time periods for the first memory cells and the second memory cells.
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