| CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/3459 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06562 (2013.01)] | 13 Claims |

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1. An apparatus comprising:
one or more control circuits configured to connect to a memory structure comprising a plurality of erase blocks having NAND memory cells, wherein the one or more control circuits are configured to:
store, for each respective erase block of the plurality of erase blocks, information that indicates whether memory cells in the respective erase block are to be programmed with program pulses having a first duration or a second duration that is longer than the first duration;
execute a first program operation that programs data into respective groups of memory cells with program pulses each having the first duration for the erase blocks for which the information indicates the first duration;
track early program terminations in the erase blocks programmed using the program pulses having the first duration, the early program termination being a termination of the first program operation before the program pulses having the first duration reach a maximum allowed magnitude despite data not yet being successfully programmed into the respective group;
report the early program terminations to a memory controller as program failures;
update the information to indicate that the second duration for the program pulses is to be used for erase blocks having more than a threshold number of early program terminations when using program pulses having the first duration; and
execute a second program operation that programs data into respective groups of the memory cells with program pulses each having the second duration for the erase blocks for which the information indicates the second duration is to be used.
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