US 12,462,876 B2
Single-level cell pump skip program operation preliminary period timing optimization for non-volatile memory
Chin-Yi Chen, San Jose, CA (US); Muhammad Masuduzzaman, Chandler, AZ (US); and Xiang Yang, Santa Clara, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 24, 2023, as Appl. No. 18/225,375.
Claims priority of provisional application 63/445,527, filed on Feb. 14, 2023.
Prior Publication US 2024/0274200 A1, Aug. 15, 2024
Int. Cl. G11C 16/00 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the strings and configured to:
successively apply one of a series of pulses of a program voltage to each selected one of the plurality of word lines to program the memory cells connected thereto during a program operation, and
utilize a time of a preliminary period of the program operation based on the one of the series of pulses of the program voltage being applied, the preliminary period of the program operation being before the series of pulses of the program voltage are applied to each selected one of the plurality of word lines,
wherein utilizing the time of the preliminary period includes, in between each of the series of pulses of the program voltage, skipping (i) a pump setting process in which a charge pump ramps up to the program voltage and (ii) a pump resetting process in which the charge pump supplies the program voltage to the plurality of word lines during the program operation and ramps down from the program voltage.