US 12,462,875 B2
Program scheme for edge data wordlines in a memory device
Hong-Yan Chen, San Jose, CA (US); and Ching-Huang Lu, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 3, 2022, as Appl. No. 17/959,171.
Claims priority of provisional application 63/281,328, filed on Nov. 19, 2021.
Prior Publication US 2023/0162796 A1, May 25, 2023
Int. Cl. G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a program voltage to be applied to a selected data wordline of a plurality of wordlines of a block of the memory array for a pulse duration period during a programming operation;
causing a first pass voltage to be applied to one or more unselected data wordlines of the plurality of wordlines of the block for the pulse duration period, wherein the one or more unselected data wordlines does not include a last unselected wordline of the plurality of wordlines; and
causing a second pass voltage to be applied to the last unselected data wordline of the plurality of wordlines of the block for at least a first portion of the pulse duration period, wherein the last unselected wordline is a last wordline of the plurality of wordlines to be programmed in a sequential programming operation, and wherein the second pass voltage has a lower magnitude than the first pass voltage.