| CPC G11C 16/0483 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); H10B 43/27 (2023.02)] | 20 Claims |
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1. A memory device, comprising:
memory cells coupled to a same word line and bit lines, respectively, wherein each of the memory cells is in one of states; and
a peripheral circuit coupled to the memory cells through the word line and the bit lines, and configured to:
determine a first number of a first set of the memory cells and a second number of a second set of the memory cells in parallel, threshold voltages of the first set of the memory cells being between a first voltage and a second voltage larger than the first voltage, threshold voltages of the second set of the memory cells being between the second voltage and a third voltage larger than the second voltage;
apply a reference voltage to the same word line to determine a first read level corresponding to a first state of the states based on the first number of the first set of the memory cells and the second number of the second set of the memory cells; and
send information associated with the first read level to a memory controller,
wherein to determine the first number of the first set of memory cells and the second number of the second set of memory cells, the peripheral circuit is configured to:
determine the first number of the first set of memory cells as a first difference between a third number of memory cells in a first reference threshold interval corresponding to the reference voltage and the first voltage and a fourth number of memory cells in a second reference threshold interval corresponding to the reference voltage and the second voltage; and
determine the second number of the second set of memory cells as a second difference between the fourth number of memory cells in the second reference threshold interval and a fifth number of memory cells in a third reference threshold interval corresponding to the reference threshold and the third voltage.
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