US 12,462,872 B2
Analog content addressable memory for general computing
Lei Zhao, Ft. Collins, CO (US); Luca Buonanno, Milpitas, CA (US); and Giacomo Pedretti, Verbania (IT)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed on Apr. 30, 2024, as Appl. No. 18/651,218.
Prior Publication US 2025/0336441 A1, Oct. 30, 2025
Int. Cl. G11C 15/04 (2006.01)
CPC G11C 15/04 (2013.01) 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first inverter;
a first sense amplifier connected to the first inverter;
a first match line connected to the first sense amplifier;
a first analog content addressable memory cell comprising:
a first pull-down transistor;
a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node;
a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and
a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.