US 12,462,870 B2
Reading a multi-level memory cell
Mattia Robustelli, Milan (IT); Fabio Pellizzer, Boise, ID (US); Innocenzo Tortorelli, Cernusco sul Naviglio (IT); and Agostino Pirovano, Milan (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 23, 2024, as Appl. No. 18/643,126.
Application 17/716,740 is a division of application No. 16/926,557, filed on Jul. 10, 2020, granted, now 11,302,390, issued on Apr. 12, 2022.
Application 18/643,126 is a continuation of application No. 17/716,740, filed on Apr. 8, 2022, granted, now 11,996,141.
Prior Publication US 2024/0321347 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/56 (2006.01); G11C 7/10 (2006.01)
CPC G11C 11/56 (2013.01) [G11C 7/1051 (2013.01); G11C 7/1096 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
applying a first read voltage with a first polarity and a first magnitude to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;
determining whether to apply a second read voltage with the first polarity and a second magnitude to the memory cell based at least in part on determining whether a first snapback event failed to occur;
determining whether to apply a third read voltage with the first polarity and a third magnitude to the memory cell based at least in part on determining whether a second snapback event failed to occur;
determining the logic state stored by the memory cell based at least in part on determining whether the first snapback event, the second snapback event, or a third snapback event occurred; and
performing a refresh operation on the memory cell after determining the logic state stored by the memory cell based at least in part on determining whether the first snapback event, the second snapback event, or the third snapback event occurred, wherein the refresh operation includes a reprogram pulse that is different from a pulse corresponding to the first read voltage, the second read voltage, or the third read voltage, wherein the reprogram pulse has a second polarity that is opposite to the first polarity, and wherein the reprogram pulse has a fourth magnitude that is less than the first magnitude, the second magnitude, or the third magnitude.