| CPC G11C 11/4096 (2013.01) [H10B 12/038 (2023.02); H10B 12/482 (2023.02); H10D 8/70 (2025.01)] | 20 Claims |
|
1. A memory structure, comprising:
a plurality of insulating layers and a plurality of gate layers that are alternately stacked;
a first doping layer penetrating through the insulating layers and the gate layers and having a first conductive type;
a plurality of second doping layers respectively in direct contact with the first doping layer and having a second conductive type different from the first conductive type, wherein the first doping layer and the second doping layers form a plurality of tunnel diodes, and the second doping layers and the insulating layers are alternately stacked;
a columnar channel penetrating through the insulating layers and the gate layers;
a plurality of third doping layers respectively surrounding the columnar channel, wherein the third doping layers are respectively connected to the second doping layers, and the third doping layers have the second conductive type;
a fourth doping layer and a fifth doping layer coupled to the columnar channel;
a first dielectric layer disposed between the first doping layer and the gate layers;
a plurality of second dielectric layers respectively disposed between the third doping layers and the gate layers;
a third dielectric layer disposed between the columnar channel and the third doping layers; and
a plurality of fourth dielectric layers respectively disposed between the second doping layers and the gate layers.
|