US 12,462,868 B2
Systems and methods for improved dual-tail latch with load control
Jinha Hwang, Boise, ID (US); and Won Joo Yun, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 10, 2023, as Appl. No. 18/506,208.
Claims priority of provisional application 63/481,484, filed on Jan. 25, 2023.
Prior Publication US 2024/0249766 A1, Jul. 25, 2024
Int. Cl. G11C 7/06 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4093 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an interface configured to receive clock signals and data signals, wherein the interface comprises a dual-tail latch comprising:
a sensing stage configured to sense and to amplify a differential voltage between at least a portion of the data signals and another signal, wherein the sensing stage comprises:
a first node;
a second node, wherein the amplified differential voltage is output from the sensing stage via the first node and the second node;
a first transistor between the first node and a supply voltage;
a second transistor between the second node and the supply voltage;
a third transistor;
a fourth transistor, wherein the third and fourth transistors form a first path through the third and fourth transistors between the first node and the supply voltage;
a fifth transistor; and
a sixth transistor, wherein the fifth and sixth transistors form a second path through the fifth and sixth transistors between the second node and the supply voltage; and
a latch stage configured to latch a first latched value and a second latched value based at least in part on the amplified differential voltage, wherein the differential voltage is based at least in part on a previous first value and a previous second value from the latch stage fed back to the sensing stage.