| CPC G11C 11/40618 (2013.01) [G11C 11/40615 (2013.01); G11C 29/20 (2013.01)] | 13 Claims |
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1. A clock signal generator, generating a clock signal;
a plurality of pulse number adjusters, coupled to the clock signal generator, receiving the clock signal, wherein during a time period, the pulse number adjusters respectively generate a plurality of adjusted clock signals by adjusting pulse number of the clock signal according to a plurality of data retention information; and
a plurality of address counters, respectively coupled to the pulse number adjusters and generating a plurality of refresh address information according to the adjusted clock signals, wherein the refresh address information correspond to a plurality of memory banks of the memory device, and the memory banks respectively perform refresh operations according to the refresh address information.
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