US 12,462,862 B2
Bank-level self-refresh
John Christopher Sancon, Boise, ID (US); Yang Lu, Boise, ID (US); Kang-Yong Kim, Boise, ID (US); Mark Kalei Hadrick, Boise, ID (US); and Hyun Yoo Lee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 21, 2022, as Appl. No. 17/660,201.
Prior Publication US 2023/0343380 A1, Oct. 26, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/40618 (2013.01); G11C 11/4085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
logic configured to:
receive, from a memory die, signaling indicative of:
a first set of at least one bank that has performed a refresh operation of a first type on a first set of at least one word line within a self-refresh mode; or
a second set of at least one bank that has not performed a refresh operation of the first type on the first set of at least one word line within the self-refresh mode;
transmit, to the memory die, signaling indicative of a command to perform a refresh operation of a second type on the first set of the at least one bank, the second type of refresh operation different from the first type of refresh operation; and
transmit, to the memory die, signaling indicative of at least one command to perform a refresh operation of the first type and a refresh operation of the second type on the second set of the at least one bank.