US 12,462,860 B2
Using split word lines and switches for reducing capacitive loading on a memory system
Sheng-Chen Wang, Hsinchu (TW); Meng-Han Lin, Hsinchu (TW); Chia-En Huang, Xinfeng Township (TW); and Yi-Ching Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 26, 2024, as Appl. No. 18/647,743.
Application 18/647,743 is a continuation of application No. 17/868,982, filed on Jul. 20, 2022, granted, now 12,002,499.
Application 17/868,982 is a continuation of application No. 17/241,263, filed on Apr. 27, 2021, granted, now 11,404,099.
Prior Publication US 2024/0274179 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/22 (2006.01); H01L 23/528 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC G11C 11/2259 (2013.01) [G11C 11/223 (2013.01); H01L 23/528 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory array comprising:
a first string of memory cells and a second string of memory cells structured parallel to the first string of memory cells;
a first switch including:
a first electrode, and
a second electrode coupled to a global bit line coupling a plurality of layers of the memory array; and
a first line coupling the first electrode of the first switch, first electrodes of respective first memory cells of the first string of memory cells, and first electrodes of respective second memory cells of the second string of memory cells.