US 12,462,858 B2
In-memory computation device having improved drift compensation
Marcella Carissimi, Treviolo (IT); Marco Pasotti, Travaco' Siccomario (IT); and Riccardo Zurla, Binasco (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Dec. 18, 2023, as Appl. No. 18/542,938.
Claims priority of application No. 102022000026760 (IT), filed on Dec. 23, 2022.
Prior Publication US 2024/0212730 A1, Jun. 27, 2024
Int. Cl. G11C 11/418 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 8/08 (2006.01); G11C 11/419 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/12 (2013.01); G11C 8/08 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An in-memory computation device, comprising:
a word line activation circuit configured to receive an input signal indicative of a plurality of input values and to provide a plurality of activation signals, wherein each activation signal is a function of a respective input value;
a biasing circuit configured to provide a bias voltage in response to a reference current;
a memory array comprising a plurality of memory cells coupled to a bit line and coupled each to a respective word line, wherein the bit line is configured to receive the bias voltage, wherein the memory cells are configured to each store a respective computational weight and to each receive a respective activation signal from the respective word line, wherein a respective cell current flows through each memory cell as a function of the bias voltage, the respective activation signal and the respective computational weight, and wherein a bit line current flows through the bit line as a function of a summation of the cell currents; and
a digital detector coupled to the bit line and configured to sample the bit line current and, in response, provide at least one output signal.