| CPC G11C 7/1087 (2013.01) [G11C 7/1057 (2013.01); G11C 7/106 (2013.01); G11C 7/1084 (2013.01)] | 20 Claims |
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1. A data serializer, comprising:
at least one data buffer, at least receiving an inputting data and a controlling signal, wherein an outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level; and
a de-skew buffer, receiving the complementary outputting signal to accelerate or slow down forming the outputting signal;
wherein each of the at least one data buffer at least includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected in series;
wherein when the controlling signal is at the predetermined level and the inputting data is a first value, the first PMOS transistor and the second PMOS transistor are turned on, so that the outputting signal is raised to a first level;
wherein when the controlling signal is at the predetermined level and the inputting data is a second value, the first NMOS transistor and the second NMOS transistor are turned on, so that the outputting signal is fallen to a second level.
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