| CPC G11C 7/1084 (2013.01) [G11C 7/1057 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01)] | 20 Claims |

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1. An apparatus, comprising:
a controller configured to provide multilevel command and address signals to a memory, the multilevel command and address signals each having a respective voltage corresponding to one of at least three or more different values, wherein the multilevel command and address signals include a memory address and a command operand, wherein the memory address corresponds to binary values and the command operand corresponds to non-binary values.
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