US 12,462,851 B2
Semiconductor device and manufacturing method of a semiconductor device
Nam Jae Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Aug. 29, 2023, as Appl. No. 18/457,351.
Claims priority of application No. 10-2023-0062767 (KR), filed on May 16, 2023.
Prior Publication US 2024/0386918 A1, Nov. 21, 2024
Int. Cl. G11C 5/00 (2006.01); G11C 5/06 (2006.01); G11C 16/08 (2006.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC G11C 5/06 (2013.01) [G11C 16/08 (2013.01); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first gate structure, comprising:
first gate lines stacked;
a first step structure including first pads stacked in a stair shape;
a first gap-fill insulating layer disposed between the first gate lines and the first step structure; and
first wiring lines stacked to electrically connect the first gate lines to respective first pads;
and
a second gate structure, comprising:
second gate lines stacked over the first gate lines;
a second step structure disposed on the first gap-fill insulating layer and including second pads stacked in a stair shape;
a second gap-fill insulating layer disposed on the first step structure; and
second wiring lines stacked to electrically connect the second gate lines to respective second pads.