| CPC G09G 5/12 (2013.01) [G02B 27/017 (2013.01); G09G 5/001 (2013.01); G02B 2027/0178 (2013.01); G09G 2310/08 (2013.01); G09G 2340/10 (2013.01); G09G 2360/04 (2013.01); G09G 2360/128 (2013.01)] | 20 Claims |

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1. A display device, comprising:
a memory operable to store at least one piece of background image data and at least one piece of region of interest (ROI) image data;
a timing controller including a scaler; and
a processor in communication with the memory and the timing controller, the processor configured to:
receive the at least one piece of background image data from the memory based on a first periodic timing signal;
receive the at least one piece of ROI image data from the memory based on a second periodic timing signal;
generate, via the scaler, a first periodic sync signal synchronized with the first periodic timing signal associated with the at least one piece of background image data;
generate, via the scaler, a second periodic sync signal synchronized with the second periodic timing signal associated with the at least one piece of ROI image data;
transmit, to the scaler, the at least one piece of background image data received from the memory during a first time period, according to the first periodic sync signal; and
transmit, to the scaler, the at least one piece of ROI image data received from the memory during a second time period, according to the second periodic sync signal.
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