| CPC G09G 3/3677 (2013.01) [G09G 3/006 (2013.01); G09G 2330/12 (2013.01)] | 16 Claims |
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1. An array substrate, comprising a display area and a non-display area surrounding the display area, wherein the non-display area consists of a gate-driver-on-array (GOA) drive circuit region, a GOA busline region, a fan-out region, and a bonding region, all positioned on a same side of the display area and sequentially arranged in a direction away from the display area; the bonding region comprises multiple bonding line groups spaced apart in succession along a first direction; the fan-out region comprises multiple source fan-out line groups and at least one first GOA signal line group; the source fan-out line groups are arranged in a one-to-one correspondence with the bonding line groups and are electrically connected to the bonding line groups; the GOA drive circuit region comprises at least one GOA drive circuit; and the GOA busline region comprises a first GOA busline line group which extends along the first direction and is electrically connected to the at least one GOA drive circuit;
wherein the array substrate further comprises a cutting region located on one side of the bonding region away from the display area, and the cutting region comprises multiple test pad units which are structurally identical and are successively spaced along the first direction; each adjacent pair of the bonding line groups is arranged corresponding to and is electrically connected to one test pad unit;
wherein the test pad units comprise a first test pad group and a second test pad group which are spaced and arranged along the first direction, a first lead group and a second lead group which are electrically connected to the first test pad group, and a third lead group electrically connected to the second test pad group; the first lead group extends from one side of the first test pad group near the bonding region; the second lead group extends from one side of the first test pad group away from the bonding region; and the third lead group extends from one side of the second test pad group near the bonding region; wherein at least one of the bonding line groups is electrically connected to the corresponding first test pad group through the adjacent first lead group; at least one of the bonding line groups is electrically connected to the corresponding first test pad group through the adjacent second lead group; and at least one of the bonding line groups is electrically connected to the corresponding second test pad group through the adjacent third lead group;
wherein each of the at least one first GOA signal line group is positioned only between adjacent source fan-out line groups, where one end of the first GOA signal line group is electrically connected to adjacent one or two of the bonding line groups, the other end of the first GOA signal line group is electrically connected to the first GOA busline line group, and the first GOA signal line group at least comprises multiple clock signal (CK) lines;
wherein each of the at least one first GOA signal line group comprises a first CK line group and a second CK line group; in the same first GOA signal line group, the first CK line group and the second CK line group are electrically connected in a one-to-one correspondence to two adjacent ones of the bonding line groups; the first GOA busline line group comprises a first CK bus line group and a second CK bus line group; each first CK line group is electrically connected to the first CK bus line group; and each second CK line group is electrically connected to the second CK bus line group.
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