| CPC G09G 3/3266 (2013.01) [G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01)] | 20 Claims |
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1. A driving circuit comprising a plurality of stages, each of the plurality of stages comprising:
a first control circuit connected to a first voltage input terminal configured to receive a first voltage and a second voltage input terminal configured to receive a second voltage lower than the first voltage, the first control circuit being configured to control voltage levels of a first control node, a second control node, and a third control node;
a first output circuit connected to a first clock terminal and a third voltage input terminal configured to receive a third voltage, the first output circuit being configured to output a first output signal from a first output node according to the voltage levels of the first control node and the second control node;
a second output circuit connected to a second clock terminal and the second voltage input terminal, the second output circuit being configured to output a second output signal from a second output node according to the voltage levels of the third control node and the second control node; and
a boosting circuit connected to a third clock terminal and the second voltage input terminal, the boosting circuit being configured to boost the voltage level of the first control node according to a signal input to the third clock terminal,
wherein the second voltage is lower than the third voltage,
wherein the third clock terminal is different from the second clock terminal, and
wherein:
the first output circuit comprises a first pull-up transistor and a first pull-down transistor, a gate of the first pull-up transistor being connected to the first control node, and a gate of the first pull-down transistor being connected to the second control node; and
the second output circuit comprises a second pull-up transistor and a second pull-down transistor, a gate of the second pull-up transistor being connected to the third control node different from the second output node, and a gate of the second pull-down transistor being connected to the second control node.
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