US 12,462,759 B2
Apparatus and method for providing power on and power off timing sequence for driving display panel
Dongxiao Shan, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 17/790,011
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Mar. 28, 2022, PCT No. PCT/CN2022/083384
§ 371(c)(1), (2) Date Jun. 29, 2022,
PCT Pub. No. WO2023/273444, PCT Pub. Date Jan. 5, 2023.
Prior Publication US 2024/0185796 A1, Jun. 6, 2024
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3233 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2330/026 (2013.01); G09G 2330/027 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus for driving a display panel, wherein the display panel comprises a pixel circuit, a gate driving circuit, a source driving circuit, and a light-emitting control driving circuit,
wherein the gate driving circuit and the source driving circuit respectively provide scan signals, data signals, to the pixel circuit;
wherein the pixel circuit includes a plurality of pixel units in an array, and each pixel unit includes an OLED element;
wherein the light-emitting control driving circuit is for outputting a light-emitting control signal to the pixel circuit;
wherein the apparatus is configured to:
during a first time period, provide an invalid start signal to the gate driving circuit and/or the light-emitting control driving circuit;
during a second time period, provide a first power signal and a second power signal to the pixel circuit;
during a third time period, provide a valid start signal to the gate driving circuit and/or the light-emitting control driving circuit;
wherein the apparatus is further configured to: during the first time period,
provide a third power signal and a fourth power signal to a power terminal of the gate driving circuit;
provide a clock signal to the gate driving circuit; and
provide an invalid first start signal to the gate driving circuit.