US 12,462,752 B2
Pixel circuit, driving method and display apparatus
Hongfei Cheng, Beijing (CN)
Assigned to Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/696,947
Filed by Beijing BOE Technology Development Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jul. 31, 2023, PCT No. PCT/CN2023/110168
§ 371(c)(1), (2) Date Mar. 28, 2024,
PCT Pub. No. WO2024/041314, PCT Pub. Date Feb. 29, 2024.
Claims priority of application No. 202211013180.8 (CN), filed on Aug. 23, 2022.
Prior Publication US 2024/0395207 A1, Nov. 28, 2024
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01); G09G 2320/045 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a light-emitting device;
a driving transistor, coupled to the light-emitting device, and configured to generate a driving current for driving the light-emitting device to emit light according to a data voltage;
a distributed capacitor, wherein a first electrode of the distributed capacitor is coupled to a gate of the driving transistor, and a second electrode of the distributed capacitor is coupled to a first electrode of the driving transistor;
an initialization circuit, configured to initialize the gate of the driving transistor under control of a signal of a reset signal terminal;
a data compensation circuit, configured to input the data voltage and compensate a threshold voltage of the driving transistor under control of a signal of a scan signal terminal; and
a light-emitting control circuit, configured to, under control of a signal of a light-emitting control signal terminal, conduct the first electrode of the driving transistor to a first power terminal, and conduct a second electrode of the driving transistor to the light-emitting device, to drive the light-emitting device to emit light;
wherein the data compensation circuit comprises a second transistor, a third transistor and a storage capacitor;
a gate of the second transistor is coupled to the scan signal terminal, a first electrode of the second transistor is coupled to a data signal terminal, and a second electrode of the second transistor is coupled to the first electrode of the driving transistor;
a gate of the third transistor is coupled to the scan signal terminal, a first electrode of the third transistor is coupled to the gate of the driving transistor, and a second electrode of the third transistor is coupled to the second electrode of the driving transistor; and
a first electrode of the storage capacitor is coupled to the gate of the driving transistor, and a second electrode of the storage capacitor is directly coupled to the first power terminal.