| CPC G09G 3/32 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] | 21 Claims |

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1. A gate driver comprising a plurality of stages, each stage of the plurality of stages comprising:
a first pull-up control circuit configured to apply a previous carry signal among carry signals of previous stages to a first control node in response to the previous carry signal;
a buffer circuit configured to output a gate clock signal as a gate output signal in response to a signal of the first control node; and
a pull-down circuit configured to output a second low voltage as the gate output signal in response to a first subsequent carry signal among carry signals of subsequent stages,
wherein the first pull-up control circuit comprises:
a 4-1st transistor comprising a control electrode configured to receive the previous carry signal, a first electrode configured to receive the previous carry signal, and a second electrode connected to a second control node;
a 4-2nd transistor comprising a control electrode configured to receive the previous carry signal, a first electrode connected to the second control node, and a second electrode connected to the first control node; and
a hold capacitor comprising a first electrode connected to the second control node and a second electrode configured to receive a constant voltage.
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