| CPC G09G 3/32 (2013.01) [G09G 3/3266 (2013.01); G11C 19/28 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2340/0435 (2013.01)] | 12 Claims |
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1. A display panel, comprising:
a driving circuit including a plurality of cascaded shift registers configured to generate a primary scanning signal;
a first display mode and a second display mode; and
a plurality of gating circuits corresponding to the plurality of shift registers, electrically connected to corresponding shift registers, and configured to generate a scanning signal,
wherein a first input terminal of a gating circuit of the plurality of gating circuits is connected to a frequency cut signal, the gating circuit is configured to control a frequency of the scanning signal in response to the frequency cut signal, and the frequency of the scanning signal is less than or equal to a frequency of the primary scanning signal,
wherein:
in the first display mode, in each display frame, a potential of the frequency cut signal is same; and
in the second display mode, in at least one display frame, the potential of the frequency cut signal jumps, and potentials of the frequency cut signals connected to at least two gating circuits of the plurality of gating circuits are different,
wherein:
the driving circuit includes a second driving circuit including a plurality of second shift registers connected in cascade and configured to generate a second primary scanning signal;
a second shift register of the plurality of second shift registers includes a fourth control module and a third output module electrically connected together;
the fourth control module receives the first voltage signal and responds to a first clock signal and a second clock signal to control a signal of a seventh node and a signal of the eighth node;
the third output module receives an input signal, the first voltage signal and the second voltage signal, and responds to the signal of the seventh node, the signal of the eighth node, the first clock signal and the second clock signal to control the second primary scanning signal;
the gating circuit includes a second gating circuit corresponding to the second shift register, electrically connected to the corresponding second shift register and configured to generate a second scanning signal; and
the second gating circuit receives the first voltage signal and controls the second scanning signal in response to the signal of the seventh node, the signal of the eighth node, the second clock signal and the frequency cut signal,
wherein:
the second gating circuit includes a fifth control module and a fourth output module;
the fifth control module responds to the frequency cut signal and the signal of the eighth node to control a signal of a ninth node; and
the fourth output module receives the first voltage signal and controls the second scanning signal in response to the signal of the seventh node, the signal of the ninth node and the second clock signal, and
wherein:
the fifth control module includes a tenth transistor and an eleventh transistor, a gate of the tenth transistor is connected to the frequency cutting signal, a source of the tenth transistor is electrically connected to the eighth node, a drain of the tenth transistor is electrically connected to the ninth node, a gate of the eleventh transistor is electrically connected to the eighth node, a source of the eleventh transistor is connected to the frequency cutting signal, and a drain of the eleventh transistor is electrically connected to the ninth node; and
the fourth output module includes a twelfth transistor and a thirteenth transistor, a gate of the twelfth transistor is electrically connected to the seventh node, and a source of the twelfth transistor is connected to the first voltage signal, a drain of the twelfth transistor is connected to the second scanning signal, a gate of the thirteenth transistor is electrically connected to the ninth node, a source of the thirteenth transistor is connected to the second clock signal, and a drain of the thirteenth transistor is connected to the second scanning signal.
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