| CPC G09G 3/32 (2013.01) [G09G 3/3266 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01)] | 17 Claims |
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1. A display panel, comprising:
a display part; and
a gate driving circuit, located on a side of the display part, wherein the gate driving circuit comprises:
N cascaded GOA (Gate On Array) units, disposed along a first direction; wherein each of the N cascaded GOA units comprises:
a signal generation module,
a first output module, comprising:
a first buffer unit, comprising:
a first output transistor, having a first active part that is a metal oxide semiconductor;
a second buffer unit, comprising:
a second output transistor having a second active part that is a low temperature polysilicon semiconductor;
wherein the first buffer unit and the second buffer unit are disposed along a second direction, and
a second output module, comprising:
a third output transistor having a third active part that is a low temperature polysilicon semiconductor;
a fourth output transistor having a fourth active part that is a low temperature polysilicon semiconductor;
wherein the signal generation module, the first output module, and the second output module are disposed along the second direction;
wherein the first output module is disposed on a side of the signal generation module close to the display part, and the first output module is configured to output a first gate driving signal;
wherein the second output module is disposed on a side of the signal generation module opposite to the side of the signal generation module close to the display part, the second output module is configured to output a second gate driving signal, and the first gate driving signal is different from the second gate driving signal;
wherein in the second direction, lengths of the first output module and the second output module are different, the second direction is parallel to scan lines of the display panel, an angle between the first direction and the second direction is greater than 0° and less than or equal to 90°, and wherein N is a positive integer;
wherein the first buffer unit is disposed close to the signal generation module, and the second buffer unit is disposed away from the signal generation module;
wherein in the second direction, a length of the first output transistor is greater than a length of the second output transistor;
wherein the third output transistor and the fourth output transistor are disposed in parallel along the first direction;
wherein a first gate of the first output transistor and a second gate of the second output transistor are connected to a first node of the signal generation module, a first source of the first output transistor is connected to a first high potential line, a first drain of the first output transistor and a second source of the second output transistor are connected to a first signal output terminal, and a second drain of the second output transistor is connected to a first low potential line; and
wherein a third gate of the third output transistor is connected to a second node of the signal generation module, a third source of the third output transistor is connected to a first clock signal line, a third drain of the third output transistor and a fourth source of the fourth output transistor are connected to a second signal output terminal, a fourth gate of the fourth output transistor is connected to a third node of the signal generation module, and a fourth drain of the fourth output transistor is connected to a second high potential line.
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