US 12,462,729 B2
Mux-free architecture for pixel data bus latching in foveated displays
Young Don Bae, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 8, 2024, as Appl. No. 18/407,193.
Prior Publication US 2025/0225909 A1, Jul. 10, 2025
Int. Cl. G09G 5/22 (2006.01); G09G 3/20 (2006.01); G09G 3/3275 (2016.01); G09G 3/36 (2006.01)
CPC G09G 3/2096 (2013.01) [G09G 5/227 (2013.01); G09G 3/2092 (2013.01); G09G 3/3275 (2013.01); G09G 3/3688 (2013.01); G09G 2310/0275 (2013.01); G09G 2340/0407 (2013.01); G09G 2354/00 (2013.01); G09G 2370/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic display, comprising:
a timing controller configured to output adjusted foveated image data to a data bus, the data bus comprising a plurality of lines; and
a first plurality of source latches directly coupled to a first line of the plurality of lines and configured to receive the adjusted foveated image data via a data pathway without a multiplexer between the timing controller and the source latches.