| CPC G09G 3/20 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/02 (2013.01); G09G 2330/021 (2013.01)] | 18 Claims |
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1. A display panel, comprising:
a display region and a non-display region at least partially surrounding the display region;
a plurality of scan lines located in the display region; and
gate drive unit groups located in the non-display region,
wherein the gate drive unit groups comprises at least one first gate drive unit group and at least one second gate drive unit group, a first gate drive unit group of the at least one first gate drive unit group comprises a plurality of first gate drive units which are cascaded, a second gate drive unit group of the at least one second gate drive unit group comprises a plurality of second gate drive units which are cascaded, the plurality of first gate drive units and the plurality of second gate drive units are connected to different scan lines of the plurality of scan lines for transmitting scan signals to the different scan lines, and one of the scan signals comprises an effective level signal; and
a period during which a first gate drive unit of the plurality of first gate drive units at a first stage transmits the effective level signal to a respective scan line of the plurality of scan lines is a first period, and a period during which a second gate drive unit of the plurality of second gate drive units at a first stage transmits the effective level signal to a respective scan line of the plurality of scan lines is a second period, wherein the first period and the second period overlap, overlap duration of the first period and the second period is t, and t>0;
wherein the single first gate drive unit comprises a first driver circuit and a second driver circuit, and the single second gate drive unit comprises a third driver circuit and a fourth driver circuit:
wherein each of one of the plurality of the first gate drive units and one of the plurality of the second gate drive units comprises a scan control circuit, a node control circuit, a reset circuit, a first stage output circuit, a first output circuit, and a second output circuit, and the scan control circuit is connected to the node control circuit, the reset circuit, a forward input terminal, an inverse input terminal, a forward scan signal terminal, an inverse scan signal terminal, a first input terminal, and a second input terminal; the first stage output circuit is electrically connected to the node control circuit, the first output circuit, the second output circuit, and a first stage terminal; the node control circuit is further electrically connected to the reset circuit, the first output circuit, and the second output circuit; the reset circuit is further electrically connected to a second level terminal; and the first output circuit is further connected to a third input terminal and a first output terminal, and the second output circuit is further connected to a fourth input terminal and a second output terminal,
wherein in the one first gate drive unit, a first driver circuit and a second driver circuit share the scan control circuit, the node control circuit, the reset circuit, and the first stage output circuit, the first driver circuit further comprises the first output circuit, and the second driver circuit further comprises the second output circuit; and
wherein in the one second gate drive unit, a third driver circuit and a fourth driver circuit share the scan control circuit, the node control circuit, the reset circuit, and the first stage output circuit, the third driver circuit further comprises the first output circuit, and the fourth driver circuit further comprises the second output circuit.
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