| CPC G06T 15/005 (2013.01) [G06T 1/20 (2013.01)] | 26 Claims |
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1. An apparatus for graphics processing, comprising:
at least one memory; and
at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to:
detect an existence of a shader termination construct for at least one graphics shader;
perform a first static analysis for an identification of a set of suitable candidates for a control flow delinearization associated with the shader termination construct;
perform a second static analysis for a cost modeling procedure for the set of suitable candidates for the control flow delinearization;
select, based on the cost modeling procedure, a candidate of the set of suitable candidates for the control flow delinearization; and
provide an indication of the selected candidate of the set of suitable candidates for the control flow delinearization,
wherein to perform the second static analysis for the cost modeling procedure, the at least one processor, individually or in any combination, is configured to:
encode a cost for each of the set of suitable candidates based on a set of characteristics of one or more if-conditionals in a set of suitable branch instructions associated with the control flow delinearization; and
encode a set of deemed benefits from the control flow delinearization for one or more selected hardware targets.
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