US 12,462,421 B2
Apparatus including NPU operated based on machine codes corresponding to ANN model
Ha Joon Yu, Seongnam-si (KR); You Jun Kim, Suwon-si (KR); and Lok Won Kim, Seongnam-si (KR)
Assigned to DEEPX CO., LTD., Seongnam-si (KR)
Filed by DEEPX CO., LTD., Seongnam-si (KR)
Filed on Mar. 12, 2024, as Appl. No. 18/602,143.
Application 18/602,143 is a continuation of application No. 18/317,642, filed on May 15, 2023, granted, now 11,948,326.
Claims priority of application No. 10-2022-0178092 (KR), filed on Dec. 19, 2022.
Prior Publication US 2024/0221204 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 7/00 (2017.01); G06T 3/40 (2006.01); G06T 7/11 (2017.01); G06T 7/20 (2017.01); G06T 7/70 (2017.01); G06V 10/764 (2022.01); G06V 10/771 (2022.01); H04N 23/61 (2023.01); H04N 23/67 (2023.01); H04N 23/69 (2023.01); H04N 23/695 (2023.01)
CPC G06T 7/70 (2017.01) [G06T 3/40 (2013.01); G06T 7/11 (2017.01); G06T 7/20 (2013.01); G06V 10/764 (2022.01); G06V 10/771 (2022.01); H04N 23/61 (2023.01); H04N 23/67 (2023.01); H04N 23/69 (2023.01); H04N 23/695 (2023.01); G06T 2207/20084 (2013.01); G06V 2201/07 (2022.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one camera;
a memory configured to store a plurality of machine codes compiled for a plurality of artificial neural network (ANN) models;
a first semiconductor chip, provided for a neural processing unit (NPU), including:
a first circuitry provided for an internal memory configured to store an input feature map and an output feature map,
a second circuitry provided for a direct memory access (DMA) configured to access and control the first circuitry,
a third circuitry provided for a plurality of processing elements (PEs) configured to process an operation of each ANN model, based on a machine code and the input feature map, and to output the output feature map, and
a fourth circuitry provided for a controller configured to control the first circuitry, the second circuitry and the third circuitry;
a second semiconductor chip, provided for a central processing unit (CPU), connected to the memory and the first semiconductor chip and configured to select the machine code in the memory; and
a signal generator configured to generate a signal applicable to control the at least one camera,
wherein when at least one object is detected or tracked with a confidence level lower than a corresponding threshold, the signal is generated to include a coordinate of the at least one object.