US 12,462,346 B2
Machine learning based noise reduction circuit
Maxim Smirnov, San Jose, CA (US); David R. Pope, Campbell, CA (US); Henryk K. Blasinski, Lodz (PL); and Kaiming Liu, Cupertino, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/692,574.
Prior Publication US 2023/0289923 A1, Sep. 14, 2023
Int. Cl. G06T 5/70 (2024.01); G06T 3/40 (2024.01); G06V 10/764 (2022.01)
CPC G06T 5/70 (2024.01) [G06T 3/40 (2013.01); G06V 10/764 (2022.01)] 20 Claims
OG exemplary drawing
 
1. A noise reduction circuit, comprising:
a hybrid kernel calculation circuit configured to:
receive, for each pixel of a version of an image, a respective patch of the image of each pixel comprising each pixel as a central pixel in the respective patch of the image and other pixels within a defined vicinity surrounding the central pixel, wherein the version of the image is selected from an image pyramid, comprising a plurality of downscaled versions of the image or an unscaled version of the image generated for the image, stored in a memory device; and
generate, for each pixel of the version of the image by processing the respective patch of the image of each pixel, a hybrid kernel by combining a machine learning (ML) kernel of each pixel of the image generated using at least one ML filter bank associated with the version of the image and a bilateral kernel of each pixel of the image; and
a noise filtering circuit coupled to the hybrid kernel calculation circuit, the noise filtering circuit configured to perform, for each pixel of the image, noise filtering of the image by convolving pixel values of the respective patch of the image with kernel coefficients of the hybrid kernel for each pixel of the image to generate a de-noised version of the image.