US 12,462,328 B2
Coordination and increased utilization of graphics processors during inference
Abhishek R. Appu, El Dorado Hills, CA (US); Altug Koker, El Dorado Hills, CA (US); John C. Weast, Portland, OR (US); Mike B. Macpherson, Portland, OR (US); Linda L. Hurd, Cool, CA (US); Sara S. Baghsorkhi, San Jose, CA (US); Justin E. Gottschlich, Santa Clara, CA (US); Prasoonkumar Surti, Folsom, CA (US); Chandrasekaran Sakthivel, Sunnyvale, CA (US); Liwei Ma, Beijing (CN); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Kamal Sinha, Cordova, CA (US); Joydeep Ray, Folsom, CA (US); Balaji Vembu, Folsom, CA (US); Sanjeev Jahagirdar, Folsom, CA (US); Vasanth Ranganathan, EL Dorado Hills, CA (US); and Dukhwan Kim, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 13, 2023, as Appl. No. 18/351,898.
Application 18/351,898 is a continuation of application No. 17/871,781, filed on Jul. 22, 2022, granted, now 11,748,841.
Application 17/871,781 is a continuation of application No. 17/143,805, filed on Jan. 7, 2021, granted, now 11,430,082, issued on Aug. 30, 2022.
Application 17/143,805 is a continuation of application No. 16/377,315, filed on Apr. 8, 2019, granted, now 10,891,707, issued on Jan. 12, 2021.
Application 16/377,315 is a continuation of application No. 15/495,054, filed on Apr. 24, 2017, granted, now 10,304,154, issued on May 28, 2019.
Prior Publication US 2024/0013337 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/20 (2006.01); G06F 9/46 (2006.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01)
CPC G06T 1/20 (2013.01) [G06F 9/46 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06N 3/044 (2023.01); G06N 3/084 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more processors, including a graphics processor, the one or more processors to:
detect, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network;
analyze the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks;
configure the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks; and
monitor utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjust allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.