US 12,462,326 B2
Method and apparatus for buffer sharing
Zhifang Long, Shanghai (CN); Yejun Guo, Shanghai (CN); Jiang Ji, Shanghai (CN); Yu Wang, Shenyang (CN); and Wenju He, Shanghai (CN)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 31, 2023, as Appl. No. 18/162,376.
Application 18/162,376 is a continuation of application No. 17/126,856, filed on Dec. 18, 2020, granted, now 11,574,381.
Claims priority of application No. 202010254401.5 (CN), filed on Apr. 2, 2020.
Prior Publication US 2023/0267568 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/20 (2006.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/5027 (2013.01); G06F 9/5061 (2013.01); G06F 9/544 (2013.01); G06T 1/60 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processing circuitry coupled to a memory, the processing circuitry to:
compare a first buffer mapped by first graphics data with a second buffer mapped by second graphics data;
remap the second graphics data to the first buffer when the first buffer is identical to the second buffer; and
switch a first buffer indicator associated with the first buffer with a second buffer indicator associated with the second buffer.