US 12,462,323 B2
Shared dynamic buffer in image signal processor
Ashwin S. Subramanian, San Jose, CA (US); Damon W Finney, San Jose, CA (US); Marc A Schaub, Sunnyvale, CA (US); Albert C Kuo, Palo Alto, CA (US); Paul S Serris, San Jose, CA (US); and Richard L Schober, Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 15, 2022, as Appl. No. 17/694,670.
Prior Publication US 2023/0298124 A1, Sep. 21, 2023
Int. Cl. G06T 1/20 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01); G06T 1/60 (2006.01); H04N 19/152 (2014.01); H04N 19/176 (2014.01)
CPC G06T 1/20 (2013.01) [G06F 13/28 (2013.01); G06F 13/4031 (2013.01); G06T 1/60 (2013.01); H04N 19/152 (2014.11); H04N 19/176 (2014.11); G06F 2213/2806 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An image signal processor, comprising:
image processing circuits configured to perform operations associated with image signal processing;
a buffer configured to buffer data between the image processing circuits and a system memory, the buffer comprising a shared section dynamically allocated among the image processing circuits; and
a rate limiter circuit coupled to the image processing circuits, the rate limiter circuit configured to arbitrate allocation of the shared section among the image processing circuits, wherein arbitrating the allocation of the shared section comprises:
allocating a number of data credits for the shared section to one of the image processing circuits;
determining total allocated blocks for the shared section allocated to the one of the image processing circuits, the total allocated blocks comprising a first number of blocks allocated for pending requests made by the one of the image processing circuits that have not received a response from the system memory, and a second number of blocks storing data received from the system memory and pending to be consumed by the one of the image processing circuits; and
reducing or preventing allocation of additional data credits separated from the number of data credits already allocated to the one of the image processing circuits for at least a duration in which the total allocated blocks occupied by the one of the image processing circuits exceed a throttling threshold responsive to determining that the total allocated blocks exceed the throttling threshold.