US 12,462,184 B2
Apparatus and method for efficient and scalable quantum instruction implementation for a high sensitivity silicon spin qubit readout
Nader Khammassi, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,480.
Prior Publication US 2023/0196176 A1, Jun. 22, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 1/02 (2006.01); G06N 10/80 (2022.01)
CPC G06N 10/80 (2022.01) [G06F 1/022 (2013.01); G06F 9/30145 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
first circuitry to process a quantum readout instruction to read states of one or more qubits of a quantum processor, the quantum readout instruction comprising instruction fields including a first one or more fields to identify a first target qubit and a second one or more fields to indicate parameters to produce one or more synthesized waveforms; and
second circuitry coupled to the first circuitry, the second circuitry to be configured based on the parameters and to perform a measurement of the first target qubit responsive to the quantum readout instruction, the second circuitry comprises:
waveform synthesis circuitry to produce a synthesized waveform based on the parameters, and to transmit the synthesized waveform to a matching network associated with the first target qubit to produce a reflected waveform; and
detection circuitry to identify differences between the reflected waveform and the synthesized waveform to determine a state associated with the first target qubit.