US 12,462,150 B2
Modular analog multiplier-accumulator unit element for multi-layer neural networks
Martin Kraemer, Mountain View, CA (US); Ryan Boesch, Louisville, CO (US); and Wei Xiong, Mountain View, CA (US)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Redpine Signals, Inc., San Jose, CA (US)
Filed on Oct. 31, 2021, as Appl. No. 17/515,523.
Prior Publication US 2023/0146445 A1, May 11, 2023
Int. Cl. G06N 3/065 (2023.01); G06F 7/544 (2006.01); G06N 3/04 (2023.01)
CPC G06N 3/065 (2023.01) [G06F 7/5443 (2013.01); G06N 3/04 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A multi-layer modular neural network comprising:
a plurality of analog multiplier-accumulator (AMAC) cells, each AMAC cell having an input and generating n feature maps (fmaps) as an AMAC cell output, each AMAC cell comprising an analog multiplier-accumulator accumulating a charge proportional to a multiplication of an AMAC cell input with a weight, adjusting the accumulated charge with a bias, and generating a digital AMAC cell output by digitizing the adjusted accumulated charge;
a first layer providing n feature maps, the first layer comprising a first layer AMAC cell, with the first layer AMAC cell output coupled to a first layer output;
a second layer providing 2*n feature maps, the second layer comprising a second layer first AMAC cell and a second layer second AMAC cell, an input of the second layer first AMAC cell and an input of the second layer second AMAC cell coupled to the first layer output, the second layer first AMAC cell digital output and the second layer second AMAC cell digital output summed to provide a second layer output;
a third layer providing 4*n feature maps, the third layer comprising a third layer first AMAC cell, a third layer second AMAC cell, a third layer third AMAC cell, and a third layer fourth AMAC cell, the third layer first AMAC cell input, third layer second AMAC cell input, third layer third AMAC cell input, and third layer fourth AMAC cell input coupled to the second layer output, the third layer having an adder generating a third layer output from a sum of the third layer first AMAC cell output, the third layer second AMAC cell output, the third layer third AMAC cell output, and the third layer fourth AMAC cell output.