US 12,462,088 B2
Chip design verification system, chip design verification method, and computer readable recording media with stored program
Xiang-Hua Shen, Suzhou (CN); Dong Qiu, Suzhou (CN); Zhong-Ying Yu, Suzhou (CN); and Chun-Yi Zhou, Suzhou (CN)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Jul. 15, 2022, as Appl. No. 17/865,593.
Claims priority of application No. 202111562327.4 (CN), filed on Dec. 20, 2021.
Prior Publication US 2023/0195994 A1, Jun. 22, 2023
Int. Cl. G06F 30/398 (2020.01)
CPC G06F 30/398 (2020.01) 15 Claims
OG exemplary drawing
 
1. A chip design verification system adapted to verify a module under test, wherein the module under test comprises: a one-time programmable module comprising a plurality of storage space modules, and each of the storage space modules has a number; a register module comprising a plurality of registers; and a register controller circuit;
the chip design verification system comprises:
an agent module comprising a sequencer module and a driver module, wherein the sequencer module is configured to enable a sequence module to generate a plurality of test data sets, and each of the test data sets comprises a location data and a specific written data; and
a result verification module coupled to the agent module and the module under test;
wherein the chip design verification system is configured to perform the following steps:
transmitting, by the driver module, the test data sets to the result verification module and performing, by the driver module, a write procedure so as to write the test data sets into the storage space modules;
performing, by the module under test, an autoload function so as to load the test data sets stored in the storage space modules into the registers correspondingly; and
reading, by the result verification module, a plurality of first readout values corresponding to the test data sets at the registers according to the location data of each of the test data sets and comparing, by the result verification module, the test data sets with the first readout values so as to determine whether the autoload function is normal; wherein the chip design verification system is configured to further perform the following steps:
performing, by the driver module, the write procedure to write the test data sets into the storage space modules of the one-time programmable module, and transmit a plurality of write commands corresponding to the write procedure and a plurality of write data values corresponding to the write commands to the result verification module;
transmitting, by the driver module, an excitation signal to the register controller circuit to make the module under test to perform a re-autoload function so as to load the test data sets stored in the storage space modules into the registers;
reading, by the result verification module, a plurality of second readout values corresponding to the write data values at the registers according to the write data values corresponding to the write commands after the module under test enters a steady state; and
determining, by the result verification module, whether the re-autoload function is normal according to the write commands, the write data values corresponding to the write commands, and the second readout values.