US 12,462,087 B2
Failsafe circuit, layout, device, and method
Zhen Tang, Hsinchu (TW); Lei Pan, Hsinchu (TW); and Miranda Ma, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed on Feb. 8, 2022, as Appl. No. 17/667,478.
Application 17/667,478 is a continuation of application No. 16/237,165, filed on Dec. 31, 2018, granted, now 11,263,380.
Claims priority of application No. 201811051924.9 (CN), filed on Sep. 10, 2018.
Prior Publication US 2022/0164517 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/398 (2020.01); G03F 1/36 (2012.01); G03F 1/70 (2012.01); G05F 1/625 (2006.01)
CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); G03F 1/70 (2013.01); G05F 1/625 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a reference node configured to carry a reference voltage level;
a first node configured to carry an input signal having a first voltage level or the reference voltage level;
a second node configured to carry a power supply voltage;
a voltage regulator comprising a source follower configured to output a gate signal having a fractional value of the input signal;
a first control circuit configured to select the higher of the power supply voltage or the gate signal as a first control signal;
a second control circuit configured to select the higher of the input signal or the first control signal as a second control signal; and
first and second transistors coupled in series between the first node and the reference node, each transistor of the first and second transistors being configured to receive a corresponding control signal of the first and second control signals.