US 12,462,084 B2
Power envelope analysis for the thermal optimization of multi-chip modules
Chien Ouyang, Pleasanton, CA (US); Xiao Gu, JiangSu (CN); Yonghyuk Jeong, Incheon (KR); and Michael Mingliang Liu, Fullerton, CA (US)
Assigned to STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed by STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed on Jul. 28, 2022, as Appl. No. 17/815,732.
Prior Publication US 2024/0037308 A1, Feb. 1, 2024
Int. Cl. G06F 30/30 (2020.01); G06F 17/16 (2006.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); H01L 23/427 (2006.01); H01L 25/16 (2023.01); G06F 113/18 (2020.01); G06F 115/06 (2020.01); G06F 115/12 (2020.01); G06F 119/02 (2020.01); G06F 119/06 (2020.01); G06F 119/08 (2020.01); G06F 119/22 (2020.01); H01L 23/00 (2006.01)
CPC G06F 30/373 (2020.01) [G06F 17/16 (2013.01); G06F 30/367 (2020.01); H01L 23/427 (2013.01); H01L 25/162 (2013.01); H01L 25/165 (2013.01); G06F 2113/18 (2020.01); G06F 2115/06 (2020.01); G06F 2115/12 (2020.01); G06F 2119/02 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01); G06F 2119/22 (2020.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1616 (2013.01); H01L 2924/16196 (2013.01); H01L 2924/16235 (2013.01); H01L 2924/16251 (2013.01); H01L 2924/1627 (2013.01); H01L 2924/351 (2013.01); H01L 2924/37001 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, comprising:
calculating a thermal resistance matrix for the semiconductor device;
selecting a plurality of maximum junction temperatures for a plurality of die of the semiconductor device;
calculating a plurality of power envelope surfaces for the semiconductor device based on the thermal resistance matrix and maximum junction temperatures;
selecting a plurality of powers for the plurality of die; and
comparing the plurality of powers against the plurality of power envelope surfaces to determine a plurality of risk values.