| CPC G06F 30/323 (2020.01) [G06N 3/0455 (2023.01)] | 7 Claims |
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1. An AI-based automated circuit generation method, comprising:
obtaining design metrics and storing the design metrics as structured data; wherein the design metrics comprise circuit performance metrics, component metrics, circuit type metrics, and component connection methods;
capturing a dependency relationship among design metrics by using an attention mechanism, extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit, and matching the high-level feature representation with a standard circuit netlist template based on the overall structure of the circuit to obtain a current circuit netlist;
simulating the current circuit netlist to obtain a simulation report, and extracting error information from the simulation report; and
correcting the current circuit netlist based on the error information, simulating a corrected circuit netlist again, looping several times until there are no errors in the simulation report, and outputting a final circuit netlist;
wherein the extracting features by using a multi-layer Transformer structure to obtain an overall structure and a high-level feature representation of a circuit comprises:
a first-layer Transformer structure, used to extract a local parameter relationship based on the dependency relationship among the design metrics;
a second-layer Transformer structure, used to extract global features based on the local parameter relationship; and
a third-layer Transformer structure, used to extract the overall structure and the high-level feature representation of the circuit based on global features, combined with circuit templates and historical circuit design cases;
wherein the obtaining a current circuit netlist comprises:
calculating relevant weights of the design metrics by using normalization operation according to the structured data:
 wherein wi is a relevant weight of an ith design metric; si is an initial weight score of a ith design metric; T is a temperature coefficient; sj is an initial weight score of a jth design metric;
calculating a dependency relationship among design metrics by using an attention mechanism:
 wherein Attention (Q, K, V) is a dependency relationship between a current design metric and all design metrics; soft max is an activation function; Q is a query matrix, which represents the current design metric; K is a key matrix, which is composed of various design metrics; dk is a key dimension; B is a bias term; V is a value matrix, which represents a weight vector related to the design metric; T is transpose;
extracting features by using a multi-layer Transformer structure according to the dependency relationship among design metrics to obtain an overall structure and a high-level feature representation of a circuit;
calculating matching scores of features in the high-level feature representation and embedded representations in the standard circuit netlist template, and extracting embedded representations of which matching scores are greater than a threshold to obtain a matching template set; and
based on the overall structure of the circuit, selecting any one embedded representation from the matching templates of features in the high-level feature representation, and obtaining the current circuit netlist based on the embedded representations selected corresponding to the features.
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