US 12,462,082 B2
Satisfying circuit design constraints using a combination of machine learning models
Satish Bachina, Hyderabad (IN); Karthic P, Chennai (IN); Vishal Tripathi, Kanpur (IN); and Srinivasan Dasasathyan, Secunderabad (IN)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Oct. 3, 2022, as Appl. No. 17/959,038.
Prior Publication US 2024/0111932 A1, Apr. 4, 2024
Int. Cl. G06F 30/32 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/3323 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/042 (2023.01); G06N 3/08 (2023.01); G06N 5/01 (2023.01); G06N 5/02 (2023.01); G06N 5/04 (2023.01); G06N 7/01 (2023.01); G06N 7/02 (2006.01); G06N 20/00 (2019.01); G06F 30/27 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/32 (2020.01) [G06F 30/27 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/3323 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06N 3/042 (2023.01); G06N 3/08 (2013.01); G06N 5/01 (2023.01); G06N 5/02 (2013.01); G06N 5/04 (2013.01); G06N 7/01 (2023.01); G06N 7/023 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
identifying features of a circuit design produced by a design tool from processing the circuit design through a first phase of a plurality of phases of an implementation flow;
applying a plurality of classifier models to the identified features produced by the design tool, wherein each classifier model is associated with a directive of a plurality of directives, the plurality of directives are associated with a second phase of the implementation flow, each directive specifies a set of parameter settings for the second phase, and each classifier model returns a value indicative of whether or not application of the associated directive is likely to improve a quality metric;
applying regressor models of each set of a plurality of sets of regressor models to the features by the design tool, wherein each directive is associated with a set of the plurality of sets of regressor models, and a respective combined score from each set of regressor models indicates a likelihood of satisfying a design constraint by the associated directive;
ranking the directives based on the values indicated by the classifier models and scores from the sets of regressor models; and
processing the circuit design in the second phase of the implementation flow by the design tool using the directive having the highest rank.